• SystemVerilog Testbench with driver and monitor for FIFO memory

    Here is an example code for testing FIFO memory with a semi structural systemverilog testbench with a generator, driver, and monitor. Verilog code for FIFO and its interface: Base class for Transaction: Base class for components: Transaction class: Generator class: Driver class: Monitor class: Environment class: Putting them all in a package: Including and importing…

  • Copy, Shallow Copy and Deep Copy in SystemVerilog

    Here, we see different nuances in copying one class to another in SystemVerilog. Copy – Assignment: Consider two classes – class lion and class zoo, class zoo is an aggregate class with a class lion in it. After assigning z2 = z1, two handles z1 and z2 created for the same memory location. Log message:…

  • Inheritance in SystemVerilog Classes

    Inheritance is a concept of creating an extended class extending from an existing base class. Extended classes can access properties and methods of the base class without redefining the existing base class members. The syntax is Other terms for the base class are parent class and superclass. Other terms for the extended class are child…

  • Classes basics in SystemVerilog

    SystemVerilog supports typical Object-Oriented Programming concepts. Class is a user-defined datatype encapsulating data properties and data methods such as functions and tasks. How it differs from struct: A class is first defined which itself is a template. When a variable of a class datatype is declared, a handle to the class object is created. A…

  • fork, join, join_any, join_none in SystemVerilog

    fork-join: fork-join syntax creates threads that can be executed in parallel. In fork-join, threads that are forked are executed concurrently. The thread after fork-join stays suspended till all threads inside fork-join are completed. In this example, jobs 1, 2, and 3 are completed before job 4 begins. Log message: [0] Job 3 is running.[0] Job…

  • Variable-size arrays- Dynamic arrays and queues in SystemVerilog

    Variable-sized arrays have dynamic sizes that are set, extended, or shrunk during run time. They are not synthesizable and are used for verification. Dynamic array: Dynamic arrays are declared with variable names followed by []. No memory is allocated when declared. Memory is allocated only when it is instantiated with new[size], where size is a…

  • Arrays in SystemVerilog- Fixed-size arrays, packed and unpacked arrays

    Arrays in SystemVerilog are data structures to store a collection of elements of the same datatype. They can be single or multi-dimensional. In fixed-size arrays, dimensions are declared before compilation. Square brackets are used to represent dimensions. They can be packed or unpacked- packed dimensions are mentioned before a variable name and take contiguous memory…

  • Strings in SystemVerilog

    string is a dynamic datatype to store strings. They resize dynamically based on the length of the string. %s format specifier is used for strings. They are not synthesizeable and are used in simulation. Strings have multiple built-in functions. A few of those are given in the below example. Log message: Original dog_name: PorkChopThird character…

  • Enum datatype in SystemVerilog

    An enumeration (enum) is a custom-defined data type that restricts a variable to a predefined set of named values. Enums are designed to make code more intuitive by using descriptive names for these values. For example, an enum can be used to represent one of the states in a finite state machine, one of the…

  • Integer and real datatypes in SystemVerilog

    reg, wire, and logic: Signal modeling in Verilog uses two main datatypes, wire and reg. wire is used for connections between components such as gates or modules and is continuously driven in continuous assignment statements. Keyword assign is used in continuous assignment statements. reg is generally used for register modeling and their values are driven…

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